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Description: 8位RISC CPU的VERILOG编程 SOURCECODE-8 RISC CPU VERILOG programs SOURCECODE
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Size: 275456 |
Author: zfhustb |
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Description: RISC的指令VerilogHDL实现-RISC instructions to achieve VerilogHDL
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Size: 134144 |
Author: 王晓东 |
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Description: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
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Size: 369664 |
Author: 陈俊 |
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Description: 一个嵌入式RISC CPU 的Verilog 设计源码,可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
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Size: 128000 |
Author: 箫勇天 |
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Description: hrisc cpu,为何只有vhdl选择呢?大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
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Size: 128000 |
Author: 12 |
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Description: 一个非常简单的cpu设计的原代码,是用verilog编写的-a very simple cpu design of the original code, was prepared by the Verilog
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Size: 730112 |
Author: wanglei |
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Description: 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
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Size: 152576 |
Author: 大为 |
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Description: 流片过的risc_8051源代码
verilog语言描述的~-flow unit off risc_8051 verilog language source code described in the ~
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Size: 36864 |
Author: 李明纬 |
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Description: 精简指令cpu,用verilog编写,详细的教程-RISC cpu, using Verilog prepared and detailed tutorial
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Size: 215040 |
Author: 郑欲 |
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Description: 32位RISC单片机verilog源码内包含说明文档经过他人测试通过-32-bit RISC single-chip Verilog source code contains documentation of others after the test
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Size: 33792 |
Author: 栾日超 |
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Description: 可综合的VerilogHDL设计实例:
---简化的RISC 8位CPU设计简介---
-VerilogHDL be integrated design example:--- simplified RISC 8 bit CPU design Introduction---
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Size: 219136 |
Author: hulin |
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Description: Verilog-RISC CPU 代码
实现了简单的RISC cpu,可供初学者参考,学习硬件描述语言,及设计方法。该程序通过了modelsim仿真验证。
北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware description language, and design methods. The procedure adopted ModelSim simulation. BUAA
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Size: 9216 |
Author: sss |
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Description: 嵌入式risc处理器源码,包含设计文档,原理图,testbench,及外围接口,使用verilog实现。-Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
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Size: 129024 |
Author: 李林 |
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Description: verilog
RISC8 cpu CORE
8位RISC CPU 内核源码(VERILOG 版)-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
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Size: 80896 |
Author: likui |
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Description: 基于quartus II软件
用verilog 语言描述的精简指令CPU-quartus II verilog
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Size: 1259520 |
Author: xu |
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Description: 用Verilog 编写的8位risc cpu,行为级描述,可综合-6 bits risc cpu by Verilog
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Size: 132096 |
Author: 徐明 |
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Description: xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
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Size: 406528 |
Author: urga turg |
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Description: xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
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Size: 252928 |
Author: urga turg |
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Description: 8位risc内核源代码,内有体统框图,较其他详细。适合初学者学习-8-bit risc kernel source code, there are decency diagram, compared with other details. Suitable for beginners to learn
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Size: 77824 |
Author: lsj |
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Description: Verilog写的简单处理器QuartusII下可编译
//指令 操作码 源寄存器 目的寄存器 操作
// NOP 0000 xxxxx xxxxxx 空操作
//ADD 0001 src dest dest<=src+dest
//SUB 0010 src dest dest<=dest-src
//AND 0011 src dest dest<=src&&dest
//NOT 0100 src dest dest<=~src
//RD 0101 xxxxx dest dest<= memory[Add_R]
//WR 0110 src xxxxx memory[Add_R]<=src
//BR 0111 xxxxx xxxxx PC<=memory[Add_R]
//BRZ 1000 xxxxx xxxxx PC<=memory[Add_R]
//HALT 1111 xxxxx xxxxx 挂起至RST-Verilog写的简单处理器QuartusII下可编译
//指令 操作码 源寄存器 目的寄存器 操作
// NOP 0000 xxxxx xxxxxx 空操作
//ADD 0001 src dest dest<=src+dest
//SUB 0010 src dest dest<=dest-src
//AND 0011 src dest dest<=src&&dest
//NOT 0100 src dest dest<=~src
//RD 0101 xxxxx dest dest<= memory[Add_R]
//WR 0110 src xxxxx memory[Add_R]<=src
//BR 0111 xxxxx xxxxx PC<=memory[Add_R]
//BRZ 1000 xxxxx xxxxx PC<=memory[Add_R]
//HALT 1111 xxxxx xxxxx 挂起至RST
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Size: 328704 |
Author: 魏文沫 |
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